Physical ASIC Design Engineer

Job Description :

Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow.
*Direct contact with our customers for future projects.
*Full understanding of the complete Cadence Innovus Place&Route flow.
*Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
*Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
*Technical voice to the customer to discuss his specifications

Profile / Requirements :

*Experience in setting-up the flow for the specific library set and foundry node used
*Experience in setting-up low power design (UPF) and debug sdc file
*Knowledge in Floorplanning & power grid design for toplevel aswell as blocks
*Place, CTS & Routing
*Solve setup & hold violations
*Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS)
*Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check

About us :

We are a Belgian engineering consulting firm that assists SMEs and large industrial organizations in bringing their innovation and R&D initiatives to life.